GCSE Computer Science: CPU Architecture and Network Protocols

This material covers two named blocks of the computer systems paper that are often revised as lists of definitions, and trains them instead through short situations. It is based on the DfE GCSE subject content for computer science, which requires CPU architecture and the role of its components in the fetch-execute cycle, hardware components and embedded systems, and networks, including the concept of networking protocols and layers.

The quiz has thirteen questions. The first eight are about the processor: what the von Neumann architecture means, which part of the CPU carries out a comparison in an IF statement, what the control unit really does, the exact order of events in the fetch stage, how many cycles a 3.2 GHz processor completes each second, why a larger cache speeds up programs, which of four machines is an embedded system and which bus carries a memory address. The last five are about protocols: which email protocol keeps a mailbox the same on a phone, a laptop and a tablet, which protocol uploads a finished website, at which layer IP works and what it does, why a video call uses UDP rather than TCP, and what is gained by organising protocols in layers. Specifications differ in how much detail they want: named registers such as the program counter, MAR and MDR appear on some, for example OCR's, and UDP and the four named TCP/IP layers appear on others, for example AQA's. The material covers both, so students can skip what their board does not ask.

Every explanation says why the correct option fits and what the others describe instead. The flashcards gather the definitions: the CPU components and registers, the fetch stage, clock speed, cache, embedded systems, the buses, each protocol and the four layers.

The written work gives eight longer tasks to answer on paper, each with a model answer and the points a marker would look for: describing the fetch-decode-execute cycle, explaining the three factors in CPU performance, defining embedded systems with examples, comparing the ALU and control unit and explaining cache, recommending an email protocol for a family, naming the TCP/IP layers with a benefit of layering, comparing TCP and UDP, and explaining the von Neumann architecture and its buses.

An oral practice with an examiner is also offered: one scenario at a time, a short follow-up when an answer is thin and brief feedback at the end. The material suits Year 10 and Year 11 students preparing for the systems paper; the sibling materials in this category cover memory, storage, network types and security.

• Explain the von Neumann architecture and the roles of the ALU, control unit, clock, registers and buses
• Describe the fetch-decode-execute cycle, including the fetch stage in detail
• Explain how clock speed, cores and cache affect performance
• Identify embedded systems and their characteristics
• State the purpose of HTTP, HTTPS, FTP, SMTP, IMAP, POP, TCP, UDP and IP
• Place protocols in the four layers of the TCP/IP model and explain the benefits of layering

Practice material written by Zestly, based on the DfE GCSE subject content for computer science (CPU architecture and the fetch-execute cycle; embedded systems; networking protocols and layers) and the corresponding sections of the AQA (8525, 3.4.5 and 3.5) and OCR (J277, 1.1 and 1.3.2) GCSE Computer Science specifications.