A-Level Computer Science: Registers, Interrupts, Addressing Modes and Assembly

This material trains the processor content of A level Computer Science: what happens inside the CPU from one instruction to the next, and how assembly language instructions use it. It is for Year 12 and Year 13 students who know what a CPU is and now need the register-by-register detail that the written papers ask for.

The quiz has twelve questions. Three follow the fetch-decode-execute cycle: what happens first in the fetch stage, which register receives data from the data bus, and what a branch does to the program counter. Two are about interrupts: the order in which the processor services a higher-priority interrupt, and why the volatile environment must be saved. Two compare addressing modes, one following an indirect address through memory and one contrasting immediate with direct addressing. Two are full traces of short programs printed in the question: a Little Man Computer loop and an AQA-style assembly loop with a comparison, a conditional branch and a logical shift, each with a one-line glossary of the instructions it uses. The rest cover how many locations a 24-bit address bus can reach, how the bits of an instruction are shared between opcode and operand, and why a GPU is suited to work that applies one operation to many independent data items.

Every explanation shows the working, including what the other addressing modes would have loaded and which pass of a loop ends it.

The flashcards cover the dedicated registers (PC, MAR, MDR or MBR, CIR, accumulator, status register), the three buses, interrupt service routines and the volatile environment, the four addressing modes, opcode and operand, RISC and CISC, and the limits of adding cores.

The written work has eight longer tasks to answer on paper: the full fetch-decode-execute cycle with registers and buses, handling a printer interrupt with priorities, the value loaded by one instruction under four addressing modes, writing a Little Man Computer program that outputs the larger of two numbers, tracing an assembly loop pass by pass, the factors that affect processor performance, RISC compared with CISC, and GPUs and the limits of multicore processing. Each task has a model answer and the points a marker would look for.

There is also a short oral practice with an examiner, who gives any program or memory contents in full, accepts either board's register names and gives brief feedback at the end.

The content is based on the processor sections of the A level specifications, for example OCR H446 sections 1.1.1, 1.1.2 and 1.2.4 (registers, the fetch-decode-execute cycle, CISC and RISC, GPUs, Little Man Computer and addressing modes) and AQA 7517 section 4.7.3 (registers, instruction set, immediate and direct addressing, assembly operations and interrupts).

• Describe the fetch-decode-execute cycle in terms of the PC, MAR, MDR/MBR, CIR and buses
• Explain how interrupts are serviced and why the volatile environment is saved
• Apply immediate, direct, indirect and indexed addressing to given memory contents
• Trace and write short Little Man Computer and AQA-style assembly programs
• Relate bus widths and instruction formats to the number of addresses and opcodes
• Compare RISC and CISC and explain the uses and limits of GPUs and multiple cores

Practice material written by Zestly, based on the processor and assembly language content of the A level Computer Science specifications (for example OCR H446 sections 1.1.1, 1.1.2 and 1.2.4, and AQA 7517 section 4.7.3).